1. Field of the Invention
The invention relates to a non-volatile semiconductor memory device suitable for use in a multivalue type construction such that, for example, quartic (4 values: 2 bits) or octenary (8 values: 3 bits) data is recorded into a memory cell of a flash type and a verifying method and a reading method of such a non-volatile semiconductor memory device.
2. Description of the Related Art
A non-volatile semiconductor memory device such as a flash memory ordinarily has a binary type 15 cell structure such that data having two values of "0" and "1" is recorded into one memory cell transistor. However, in the semiconductor memory device with the binary type construction, there is a limitation in a memory capacity. Particularly, it is considered that such a semiconductor memory device is used to record video data or audio data and a memory device having a large capacity such that video data or audio data of a long time can be recorded is demanded. A method of enabling multivalue data to be recorded into one memory cell, therefore, has been proposed.
However, if a storing level for one cell is set to, for example, the quartic value (4 values) or octenary value (8 values), a problem such that a circuit for verifying and a circuit for reading become complicated and a circuit scale increases occurs.
FIG. 1 shows an example of a non-volatile semiconductor memory device in which a storing multivalue level corresponds to the quartic value and which has already been proposed by the applicant of the present invention. As shown in FIG. 1, the non-volatile semiconductor memory device is constructed by: a memory array 211; a bit line voltage generating circuit 212; and a read/verify control circuit 213.
The memory array 211 has a construction such that a plurality of memory strings are arranged in a matrix form. One memory string is connected to a bit line BL0 and the other memory string is connected to a bit line BL1.
The memory string is constructed by an NAND string in which memory cell transistors each comprising a non-volatile semiconductor memory device having a floating gate are serially connected. Drains of the memory cell transistors of the NAND string are connected to the bit lines BL0 and BL1 through selection gates, respectively. Control gates of the memory cells of the same row are connected to a common word line. Multivalue data of the quartic value is written into the memory cell on a page unit basis by using a self boost.
The bit line voltage generating circuit 212 is constructed by NMOS transistors n101 to n108 and latch circuits LQ2 and LQ1 in each of which both inputs and both outputs of inverters are coupled, respectively. Supply lines of voltages VB1 and VB2 are led out from the bit line voltage generating circuit 212.
Upon writing, a bit line voltage according to write data is generated by the bit line voltage generating circuit 212 and supplied to memory cells in the memory array 211. The latch circuits LQ2 and LQ1 are included in the bit line voltage generating circuit 212. Upon verification, storing nodes Q2 and Q1 of the latch circuits LQ2 and LQ1 of the bit line voltage generating circuit 212 are set to "11" when data is sufficiently written into the memory cell in the memory array 211. Upon reading, a threshold voltage of the memory cell in the memory array 211 is detected and data is read out. In this instance, the read data is stored into the storing nodes Q2 and Q1 of the latch circuits LQ2 and LQ1.
The read/verify control circuit 213 is constructed by NMOS transistors n109 to n119. The read/verify control circuit 213 controls states of the latch circuits LQ2 and LQ1 upon reading or verifying. Supply lines of signals .phi.LAT1 to .phi.LAT4 are led out from the read/verify control circuit 213. Pulse-like signals are supplied to the supply lines of signals .phi.LAT1 to .phi.LAT4. Gate electrodes of the NMOS transistors n109 and n110 of the read/verify control circuit 213 are connected to a node SA. The node SA becomes a node to detect the threshold voltage of the memory cell in the memory array 211.
An NMOS transistor H103 of a high withstanding voltage is connected between the node SA and bit line BL0. An NMOS transistor H104 of a high withstanding voltage is connected between the node SA and the bit line BL1. An address decoding signal AnB is supplied to a gate electrode of the NMOS transistor H103. An address decoding signal AnN is supplied to a gate electrode of the NMOS transistor H104. An NMOS transistor H101 of a high withstanding voltage is connected between a supply line of a power voltage Vcc. (for example, 3.3V) and the bit line BL0. An NMOS transistor H102 of a high withstanding voltage is connected between the supply line of the power voltage Vcc and the bit line BL1. A control signal INHB is supplied to a gate electrode of the NMOS transistor H101. A control signal INHN is supplied to a gate electrode of the NMOS transistor H102.
The NMOS transistor n102 is connected between the node SA and a ground line GND. A PMOS transistor p101 is connected between the node SA and the power voltage Vcc. A reset signal RST1 is supplied to a gate electrode of the NMOS transistor n102. A signal Vref is supplied to a gate electrode of the PMOS transistor p101.
The NMOS transistor n101 is provided between the node SA and bit line voltage generating circuit 212. That is, a drain of the NMOS transistor n101 is connected to the node SA. A source of the NMOS transistor n101 is connected to drains of the NMOS transistors n103, n105, and n107, respectively. A control signal PGM is supplied to a gate electrode of the NMOS transistor n101.
The NMOS transistors n105 and n106 are serially connected between the source of the NMOS transistor n101 and the supply line of the voltage VB1. The NMOS transistors n107 and n108 are serially connected between the source of the NMOS transistor n101 and the supply line of the voltage VB2. The NMOS transistors n103 and n104 are serially connected between the source of the NMOS transistor n101 and the ground line.
The latch circuits LQ2 and LQ1 have the storing nodes Q2 and Q1 and their inversion storing nodes /Q2 and /Q1, respectively. "/" denotes a bar indicative of the inversion.
The inversion storing node /Q2 of the latch circuit LQ2 is connected to gate electrodes of the NMOS transistors n104 and n106. The storing node Q2 of the latch circuit LQ2 is connected to a gate electrode of the NMOS transistor n108.
The inversion storing node /Q1 of the latch circuit LQ1 is connected to gate electrodes of the NMOS transistors n103 and n107. The storing node Q1 of the latch circuit LQ1 is connected to a gate electrode of the NMOS transistor n105.
The NMOS transistors n111 and n112 are connected between the storing node Q2 of the latch circuit LQ2 and the ground line and between the storing node Q1 of the latch circuit LQ1 and the ground line, respectively.
In the read/verify control circuit 213, the gate electrodes of the NMOS transistors n109 and n110 are connected to the node SA. A drain of the NMOS transistor n109 is connected to the inversion storing node /Q2 of the latch circuit LQ2. A drain of the NMOS transistor n110 is connected to the inversion storing node /Q1 of the latch circuit LQ1.
The NMOS transistors n113 and n114 which are serially connected are connected between a source of the NMOS transistor n109 and the ground line. The NMOS transistor n115 is connected in parallel to the NMOS transistor n113.
The NMOS transistors n118 and n119 are serially connected between a source of the NMOS transistor n110 and the ground line. The NMOS transistors n116 and n117 which are serially connected are connected in parallel to the NMOS transistors n118 and n119.
Supply lines of the signals .phi.LAT1 to .phi.LAT4 are led out from the read/verify control circuit 213. A gate electrode of the NMOS transistor n119 is connected to the supply line of the signal .phi.LAT1. A gate electrode of the NMOS transistor n117 is connected to the supply line of the signal .phi.LAT2. A gate electrode of the NMOS transistor n114 is connected to the supply line of the signal .phi.LAT3. A gate electrode of the NMOS transistor n113 is connected to the supply line of the signal .phi.LAT4.
The inversion storing node /Q2 of the latch circuit LQ2 is connected to a gate electrode of the NMOS transistor n116. The storing node Q2 of the latch circuit LQ2 is connected to a gate electrode of the NMOS transistor n118. The storing node Q1 of the latch circuit LQ1 is connected to a gate electrode of the NMOS transistor n115.
The storing node Q2 of the latch circuit LQ2 is connected to a data bus line through a predetermined transistor (not shown). The storing node Q1 of the latch circuit LQ1 is connected to the data bus line through a predetermined transistor (not shown).
The writing operation will now be described. In a standby mode, the signal PGM is set to the low level, the NMOS transistor n101 is held non-conductive, and the bit lines BL0 and BL1 are disconnected from the latch circuits LQ2 and LQ1 of the bit line voltage generating circuit 212.
The reset signal RST1 is set to the high level, the signals AnB and AnN are set to the level (Vcc-Vth), and the bit lines BL0 and BL1 are set to the ground level. In this instance, the signals INHB and INHN are set to the low level.
When the writing operation is activated in this state, write data from the data bus is fetched and held in the latch circuits LQ2 and LQ1.
After that, the signal RST1 is switched to the low level and the bit lines BL0 and BL1 are disconnected from the ground line. The signals AnB and AnN are set to the high level (for example, passing voltage upon reading) of Vcc or higher. The signal Vref is set to the low level. The PMOS transistor p101 is held conductive. Thus, all of the bit lines BL0 and BL1 are charged to the power voltage Vcc.
Upon writing, an address on the side which is not selected by an address signal, for example, AnN is set to the ground level and, at the same time, the control signal INHN is set to the high level of Vcc or higher. The signal PGM is set to the high level and the voltages VB2 and VB1 are set to predetermined voltages which satisfy a relation of (VB2&gt;VB1&gt;0).
When the write data is "00", the inversion nodes /Q2 and /Q1 of the latch circuits LQ2 and LQ1 are at the high level. Thus, the NMOS transistors n103 and n104 are made conductive and the bit line BL0 is set to the ground level.
When the write data is "1", the NMOS transistors n105 and n106 are made conductive and the bit line BL0 is set to the voltage VB1.
When the write data is "11", the NMOS transistors n107 and n108 are made conductive and the bit line BL0 is set to the voltage VB2.
When the write data is "10", both the path between the voltage VB2 and the ground line and the path between the voltage VB1 and the ground line are disconnected from the bit line. Thus, the voltage of the bit line is held at the Vcc level.
By the above processes, after the selection bit line BL0 was set to the voltage according to the write data, the word line is set to the writing voltage, the non-selection word line is set to the write passing voltage, and the writing operation is performed.
The verifying and reading operation will now be described with reference to a timing chart of FIG. 2. It is now assumed that the even bit line side is selected.
In the verifying operation, each time one writing operation is finished, write checks of "00", "01", and "11" are performed.
In the example, the verification is sequentially performed from the data at a higher level. That is, the word line voltage is sequentially reduced to VVF3.fwdarw.VVF2.fwdarw.VVF1 and the verification is performed. The verifying operation will now be specifically explained hereinbelow.
First, the signal Vref is set to the low level and the PMOS transistor p101 is held conductive. The signal RST1 is set to the low level and the NMOS transistor n102 is held non-conductive. The signal AnB is set to VAnB (VAnB=Vcc-Vth) and the voltage of the bit line is charged to the level dropped from the level of the signal AnB by a threshold voltage Vth' with a back bias. After that, by cutting off the NMOS transistor H103, the node SA is charged to the power voltage Vcc.
After the elapse of a predetermined time, the signal Vref is set to the voltage which enables the current enough to compensate a leak current of the bit line to be supplied to the PMOS transistor p101. A voltage P5V is set to the word line of the non-selection memory cell. The voltage VVF3 is applied to the word line to which the selection cell is connected.
First, the write data is subjected to the verification of "00". At this time, the selection word line voltage is set to VVF3.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VVF3 (Vth&gt;VVF3), since no current flows in the cell, the bit line voltage does not change, the node SA is held at the power voltage Vcc, and the NMOS transistors n109 and n110 are held conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT1, .phi.LAT3, and .phi.LAT4 are set to the high level at the timings shown in FIG. 2.
For a period of time during which the signals .phi.LAT3 and .phi.LAT4 are at the high level, both the NMOS transistors n113 and n114 are switched to the conductive state. At this time, since the NMOS transistor n109 is conductive, the inversion node /Q2 of the latch circuit LQ2 is set to the low level and the node Q2 of the latch circuit LQ2 is inverted to the high level.
For a period of time during which the signal .phi.LAT3 is at the high level, the NMOS transistor n119 is switched to the conductive state. At this time, since the gate electrode of the NMOS transistor n118 is set to the high level because the level of the node of the latch circuit LQ2 is inverted, the NMOS transistor n118 is also switched to the conductive state. The inversion node /Q1 of the latch circuit LQ1 is set to the low level and the node Q1 of the latch circuit LQ1 is inverted to the high level.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "00" is larger than the word line voltage VVF3 (Vth&gt;VVF3), the latch data of the latch circuits LQ2 and LQ1 is inverted to "11". After that, upon rewriting, the bit line BL is set to the power voltage Vcc, the channel is boosted to a non-writing potential, and no data is written.
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VVF3 (Vth&lt;VVF3), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor H103 is turned on, and redistribution of charges occurs. The electric potential of the node SA is set to (VAnB-Vth') that is almost equal to the bit line voltage. When the potential of the node SA is equal to (VAnB-Vth'), the NMOS transistors n109 and n110 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT1, .phi.LAT3, and .phi.LAT4 are set to the high level at the timings shown in FIG. 2.
For a period of time during which the signals .phi.LAT3 and .phi.LAT4 are at the high level, both the NMOS transistors n113 and n114 are switched to the conductive state. Although the NMOS transistors n113 and n114 are switched to the conductive state, since the NMOS transistor n109 is not made conductive at all, the inversion of the node of the latch circuit LQ2 does not occur.
For a period of time during which the signal .phi.LAT1 is at the high level, the NMOS transistor n119 is switched to the conductive state. At this time, since the NMOS transistor n116 is non-conductive (the inversion of the node of the latch circuit LQ2 does not occur), the inversion of the node of the latch circuit LQ1 does not occur.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "00" is smaller than the word line voltage VVF3 (Vth&lt;VVF3), the latch data of the latch circuits LQ2 and LQ1 does not change but is held to "00". Upon rewriting, the bit line voltage is set to the writing potential and the data is written.
Subsequently, the verification of the write data "01" is performed. In this instance, the selection word line voltage is set to VVF2.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VVF2 (Vth&gt;VVF2), since no current flows in the cell, the bit line voltage does not change, the node SA is held at the power voltage Vcc, and the NMOS transistors n109 and n110 are held conductive.
After the elapse of a predetermined time, the pulse-like signal .phi.LAT3 is set to the high level at the timing shown in FIG. 2.
For a period of time during which the signal .phi.LAT3 is at the high level, the NMOS transistor n114 is switched to the conductive state. At this time, since the gate electrode of the NMOS transistor n115 is set to the high level by the Q2 output of the latch circuit LQ1, the NMOS transistor n115 is also switched to the conductive state. The inversion node /Q2 of the latch circuit LQ2 is set to the low level and the node Q1 of the latch circuit LQ1 is inverted to the high level.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "01" is larger than the word line voltage VVF2 (Vth&gt;VVF2), the latch data of the latch circuits LQ2 and LQ1 is inverted to "11". After that, upon rewriting, the bit line BL is set to the power voltage Vcc, the channel is boosted to a non-writing potential, and no data is written.
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VVF2 (Vth&lt;VVF2), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor H103 is turned on, and redistribution of charges occurs. The electric potential of the node SA is set to (VAnB-Vth) that is almost equal to the bit line voltage. When the potential of the node SA is equal to (VAnB-Vth'), the NMOS transistors n109 and n110 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signal .phi.LAT3 is set to the high level at the timing shown in FIG. 2.
For a period of time during which the signal .phi.LAT3 is at the high level, the NMOS transistor n114 is switched to the conductive state. At this time, since the NMOS transistor n109 is not made conductive at all, the inversion of the node of the latch circuit LQ2 does not occur.
Subsequently, the verification of the write data "10" is performed. In this instance, the selection word line voltage is set to VVF1.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VVF1 (Vth&gt;VVF1), since no current flows in the cell, the bit line voltage does not change, the node SA is held at the power voltage Vcc, and the NMOS transistors n109 and n110 are held conductive.
After the elapse of a predetermined time, the pulse-like signal .phi.LAT1 is set to the high level at the timing shown in FIG. 2.
For a period of time during which the signal .phi.LAT1 is at the high level, the NMOS transistor n119 is switched to the conductive state. At this time, since the gate electrode of the NMOS transistor n118 is set to the high level by the Q2 output of the latch circuit LQ2, the NMOS transistor n118 is also switched to the conductive state. The inversion node /Q1 of the latch circuit LQ1 is set to the low level and the node Q1 of the latch circuit LQ1 is inverted to the high level.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "10" is larger than the word line voltage VVF1 (Vth&gt;VVF1), the latch data of the latch circuits LQ2 and LQ1 is inverted to "11". After that, upon rewriting, the bit line BL is set to the power voltage Vcc, the channel is boosted to a non-writing potential, and no data is written.
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VVF1 (Vth&lt;VVF1), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor H103 is turned on, and redistribution of charges occurs. The electric potential of the node SA is set to (VAnB-Vth') that is almost equal to the bit line voltage. When the potential of the node SA is equal to (VAnB-Vth'), the NMOS transistors n109 and n110 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signal .phi.LAT1 is set to the high level at the timing shown in FIG. 2.
For a period of time during which the signal .phi.LAT1 is at the high level, the NMOS transistor n119 is switched to the conductive state. Since the NMOS transistor n110 is not made conductive at all, the inversion of the node of the latch circuit LQ1 does not occur.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "10" is smaller than the word line voltage VVF1 (Vth&lt;VVF1), the latch data of the latch circuits LQ2 and LQ1 does not change but is held to "10". Upon rewriting, the bit line voltage is set to the writing potential and the data is written.
At the end of the verification at the word line voltage VVF1, the wired OR of the inversion signals of all latch data is calculated. If any one of them is equal to "0", the result of the wired OR is set to the low level and the processing routine advances to the rewriting process. If all of them are equal to "1", the writing operation is finished. The foregoing writing and verifying cycle is repeated until it is determined that the data has sufficiently been written into all of the memory cells or until the number of writing times reaches a predetermined value.
The reading operation will now be described with reference to a timing chart of FIG. 3. Upon reading, in a manner similar to the case of the verification, the data is read out in order from the data at a higher level. That is, the word line voltage is sequentially reduced to VRD3.fwdarw.VRD2.fwdarw.VRD1 and the data is read out. It is assumed that the even bit line side is selected.
Upon reading, first, prior to the reading operation, a signal RST2 is held at the high level for a predetermined period of time and the latch circuits LQ2 and LQ1 are reset. In a manner similar to the case of the verification, the signal Vref is set to the low level, the PMOS transistor p101 is held conductive, the signal RST1 is set to the low level, and the NMOS transistor n102 is held non-conductive. The signal AnB is set to VAnB (VAnB=Vcc-Vth). The bit line voltage is charged to the level dropped from the level of the signal AnB by the threshold voltage Vth' with the back bias. After that, by cutting off the NMOS transistor H103, the node SA is charged to the power voltage Vcc.
After the elapse of a predetermined time, the signal Vref is set to the voltage which enables the current enough to compensate a leak current of the bit line to be supplied to the PMOS transistor p101. The voltage P5V is set to the word line of the non-selection memory cell. The voltage VRD3 is applied to the word line to which the selection cell is connected.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD3 (Vth&gt;VRD3) as a result of the reading at the word line voltage VRD3, since no cell current flows, the node SA is held at the power voltage Vcc. In this instance, the NMOS transistors n109 and n110 are made conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT3, .phi.LAT4, and .phi.LAT1 are set to the high level at the timings shown in FIG. 3. The NMOS transistors n113 and n114 are made conductive.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD3, the NMOS transistor n109 is conductive. Therefore, the inversion node /Q2 of the latch circuit LQ2 is set to "0" and the node Q2 of the latch circuit LQ2 is inverted to "1".
When the signal .phi.LAT1 is set to the high level, the NMOS transistor n119 is made conductive. In this instance, since the gate electrode of the NMOS transistor n118 is set to the high level by the Q2 output of the latch circuit LQ2, the NMOS transistor n118 is also switched to the conductive state. The NMOS transistor n110 is conductive. Therefore, when the signal .phi.LAT1 is set to the high level, the inversion node /Q1 of the latch circuit LQ1 is set to "0" and the node Q1 of the latch circuit LQ1 is inverted to "1".
Thus, when the threshold voltage Vth of the memory cell is larger than the word line voltage VRD3 (Vth&gt;VRD3), the latch data of the latch circuits LQ2 and LQ1 is inverted to "11".
On the other hand, when the threshold voltage Vth of the memory cell is smaller than the word line voltage VRD3 (Vth&lt;VRD3), the cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor H103 is made conductive, and redistribution of charges occurs. The voltage of the node SA is set to (VAnB-Vth') that is almost equal to the bit line voltage. Thus, the NMOS transistors n109 and n110 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT3 and .phi.LAT4 are set to the high level and the NMOS transistors n113 and n114 are made conductive. However, since the NMOS transistor n109 is not made conductive at all, the inversion of the node of the latch circuit LQ2 does not occur.
When the signal .phi.LAT1 is set to the high level, the NMOS transistor n119 is made conductive. However, since the NMOS transistor n110 is not made conductive at all, the inversion of the node of the latch circuit LQ1 does not occur.
Subsequently, the word line voltage is set to VRD2 and the data is read out. When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD2 (Vth&gt;VRD2) as a result of the reading at the word line voltage VRD2, since no cell current flows, the node SA is held at the power voltage Vcc. In this instance, the NMOS transistors n109 and n110 are made conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT3 and .phi.LAT4 are set to the high level and the NMOS transistors n113 and n114 are made conductive. At this time, since the NMOS transistor n109 is conductive, the inversion node /Q2 of the latch circuit LQ2 is set to "0" and the node Q2 of the latch circuit LQ2 is inverted to "1".
Consequently, when the threshold voltage Vth of the memory cell is larger than the word line voltage VRD2 (Vth&gt;VRD2), the latch data of the latch circuits LQ2 and LQ1 is inverted to "10".
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VRD2 (Vth&lt;VRD2), the cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor H103 is made conductive, and redistribution of charges occurs. The voltage of the node SA is set to (VAnB-Vth) that is almost equal to the bit line voltage. Thus, the NMOS transistors n109 and n110 are not made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT3 and .phi.LAT4 are set to the high level and the NMOS transistors n113 and n114 are made conductive. However, since the NMOS transistor n109 is not made conductive at all, the inversion of the node of the latch circuit LQ2 does not occur.
Subsequently, the word line voltage is set to VRD1 and the data is read out. When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD1 (Vth&gt;VRD1) as a result of the reading at the word line voltage VRD1, since no cell current flows, the node SA is held at the power voltage Vcc. In this instance, the NMOS transistors n109 and n110 are held conductive.
After the elapse of a predetermined time, the pulse-like signal .phi.LAT2 is set to the high level and the NMOS transistor n117 is made conductive. At this time, the NMOS transistor n110 is conductive. Since the gate electrode of the NMOS transistor n116 is set to the high level by the /Q2 output of the latch circuit LQ2, the NMOS transistor n116 is also made conductive. Therefore, when the signal .phi.LAT2 is set to the high level, the inversion node /Q1 of the latch circuit LQ1 is set to "0" and the node Q1 of the latch circuit LQ1 is inverted to "1".
Consequently, when the threshold voltage Vth of the memory cell is larger than the word line voltage VRD1 (Vth&gt;VRD1), the latch data of the latch circuits LQ2 and LQ1 is inverted to "01".
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VRD1 (Vth&lt;VRDL), the cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor H103 is made conductive, and redistribution of charges occurs. The voltage of the node SA is set to (VAnB-Vth) that is almost equal to the bit line voltage. Thus, the NMOS transistors n109 and n110 are not made conductive at all.
After the elapse of a predetermined time, the pulse-like signal .phi.LAT2 is set to the high level and the NMOS transistor n117 is made conductive. However, since the NMOS transistor n110 is not made conductive at all, the inversion of the node of the latch circuit LQ1 does not occur.
FIG. 4 shows an example of a non-volatile semiconductor memory device in which the storing multivalue level corresponds to the octenary value and which has already been proposed by the applicant of the present invention. The non-volatile semiconductor memory device is constructed by: a memory array 111; a bit line voltage generating circuit 112; and a read/verify control circuit 113.
The memory array 111 has a construction such that a plurality of memory strings are arranged in a matrix form. One memory string is connected to the bit line BL0 and the other memory string is connected to the bit line BL1.
The memory string is constructed by an NAND string in which memory cell transistors each comprising a non-volatile semiconductor memory device having a floating gate are serially connected. Drains of the memory cell transistors of the NAND string are connected to the bit lines BL0 and BL1 through selection gates, respectively. Control gates of the memory cells of the same row are connected to a common word line. Multivalue data of the octenary value is written into the memory cell on a page unit basis by using a self boost.
The bit line voltage generating circuit 112 is constructed by NMOS transistors N101 to N114 and latch circuits LQ2, LQ1, and LQ0 in each of which both inputs and both outputs of inverters are coupled, respectively. Supply lines of voltages, VB0, VB1, VB2, and VB3 are led out from the bit line voltage generating circuit 112.
Upon writing, a bit line voltage according to write data is generated by the bit line voltage generating circuit 112 and supplied to memory cells in the memory array 111. The latch circuits LQ2, LQ1, and LQ0 are included in the bit line voltage generating circuit 112. Upon verification, storing nodes Q2, Q1, and Q0 of the latch circuits LQ2, LQ1, and LQ0 of the bit line voltage generating circuit 112 are set to "111" when data is sufficiently written into the memory cell in the memory array 11. Upon reading, a threshold voltage of the memory cell in the memory array 111 is detected and data is read out. In this instance, the read data is decoded and set into the storing nodes Q2, Q1, and Q0 of the latch circuits LQ2, LQ1, and LQ0.
The read/verify control circuit 113 is constructed by NMOS transistors N115 to N141. The read/verify control circuit 113 controls states of the latch circuits LQ2, LQ1, and LQ0 upon reading or verification. Supply lines of signals .phi.LAT0 to .phi.LAT9 are led out from the read/verify control circuit 113. Pulse-like signals are supplied to the supply lines of the signals .phi.LAT0 to .phi.LAT9. Gate electrodes of the NMOS transistors N115, N116, and N117 of the read/verify control circuit 113 are connected to the node SA. The node SA becomes a node to detect the threshold voltage of the memory cell in the memory array 111.
A serial connection of an NMOS transistors HN101 and HN103 of a high withstanding voltage is provided between the node SA and the bit line BL0. A serial connection of NMOS transistors HN102 and HN104 of a high withstanding voltage is provided between the node SA and the bit line BL1. An address decoding signal AiB is supplied to a gate electrode of the NMOS transistor HN103. An address decoding signal AiN is supplied to a gate electrode of the NMOS transistor HN104. A control signal TRN is supplied to gate electrodes of the NMOS transistors HN101 and HN102.
The NMOS transistor N101 is connected between the node SA and the ground line GND. The PMOS transistor P101 is connected between the node SA and the supply line of the power voltage Vcc (for example, 3.3V). A control signal DIS is supplied to the gate electrode of the NMOS transistor N101. The signal Vref is supplied to the gate electrode of the PMOS transistor P101.
The NMOS transistor N102 is provided between the node SA and bit line voltage generating circuit 112. That is, a drain of the NMOS transistor N102 is connected to the node SA. A source of the NMOS transistor N102 is connected to drains of the NMOS transistors N103, N105, N107, and N109. The control signal PGM is supplied to the gate electrode of the NMOS transistor N102.
The NMOS transistors N103 and N104 are serially connected between a source of the NMOS transistor N102 and the supply line of the voltage VB0. The NMOS transistors N105 and N106 are serially connected between the source of the NMOS transistor N102 and the supply line of the voltage VB1. The NMOS transistors N107 and N108 are serially connected between the source of the NMOS transistor N102 and the supply line of the voltage VB2. The NMOS transistors N109, N110, and N111 are serially connected between the source of the NMOS transistor N102 and the supply line of the voltage VB3.
The latch circuits LQ2, LQ1, and LQ0 have the storing nodes Q2, Q1, and Q0 and their inversion storing nodes /Q2, /Q1, and /Q0, respectively. "/" denotes a bar indicative of the inversion.
The inversion storing node /Q2 of the latch circuit LQ2 is connected to gate electrodes of the NMOS transistors N104 and N106. The storing node Q2 of the latch circuit LQ2 is connected to gate electrodes of the NMOS transistors N107 and N109.
The inversion storing node /Q1 of the latch circuit LQ1 is connected to gate electrodes of the NMOS transistors N103 and N108. The storing node Q1 of the latch circuit LQ1 is connected to gate electrodes of the NMOS transistors N105 and N110.
The inversion storing node /Q0 of the latch circuit LQ0 is connected to a gate electrode of the NMOS transistor N111.
The NMOS transistors N112, N113, and N114 are connected between the storing node Q2 of the latch circuit LQ2 and the ground line, between the storing node Q1 of the latch circuit LQ1 and the ground line, and between the storing node Q0 of the latch circuit LQ0 and the ground line, respectively. Gate electrodes of the NMOS transistors N112, N113, and N114 are connected to a supply line of a reset signal RST.
In the read/verify control circuit 113, the gate electrodes of the NMOS transistors N115, N116, and N117 are connected to the node SA. A drain of the NMOS transistor N115 is connected to the inversion storing node /Q2 of the latch circuit LQ2. A drain of the NMOS transistor N116 is connected to the inversion storing node /Q1 of the latch circuit LQ1. A drain of the NMOS transistor N117 is connected to the inversion storing node /Q0 of the latch circuit LQ0.
The NMOS transistor N118 is connected between a source of the NMOS transistor N115 and the ground line. A serial circuit of the NMOS transistors N119, N120, and N121 is connected in parallel to it.
A source of the NMOS transistor N116 is connected to a drain of the NMOS transistor N122 and a drain of the NMOS transistor N127. The NMOS transistors N123 and N124 are serially connected between a source of the NMOS transistor N122 and the ground line. A serial circuit of the NMOS transistors N125 and N126 is connected in parallel to them.
The NMOS transistors N128 and N129 are serially connected between a source of the NMOS transistor N127 and the ground line. A serial circuit of the NMOS transistors N130 and N131 is connected in parallel to them.
A source of the NMOS transistor N117 is connected to a drain of the NMOS transistor N132 and a drain of the NMOS transistor N137. The NMOS transistors N133 and N134 are serially connected between a source of the NMOS transistor N132 and the ground line. A serial circuit of the NMOS transistors N135 and N136 is connected in parallel to them.
The NMOS transistors N138 and N139 are serially connected between a source of the NMOS transistor N137 and the ground line. A serial circuit of the NMOS transistors N140 and N141 is connected in parallel to them.
Supply lines of the signals .phi.LAT0 to .phi.LAT9 are led out from the read/verify control circuit 113. A gate electrode of the NMOS transistor N118 is connected to the supply line of the signal .phi.LAT0. A gate electrode of the NMOS transistor N121 is connected to the supply line of the signal .phi.LAT1. A gate electrode of the NMOS transistor N124 is connected to the supply line of the signal .phi.LAT2. A gate electrode of the NMOS transistor N126 is connected to the supply line of the signal .phi.LAT3. A gate electrode of the NMOS transistor N129 is connected to the supply line of the signal .phi.LAT4. A gate electrode of the NMOS transistor N131 is connected to the supply line of the signal .phi.LAT5. A gate electrode of the NMOS transistor N134 is connected to the supply line of the signal .phi.LAT6. A gate electrode of the NMOS transistor N136 is connected to the supply line of the signal .phi.LAT7. A gate electrode of the NMOS transistor N139 is connected to the supply line of the signal .phi.LAT8. A gate electrode of the NMOS transistor N141 is connected to the supply line of the signal .phi.LAT9.
The inversion storing node /Q2 of the latch circuit LQ2 is connected to gate electrodes of the NMOS transistors N127 and N137. The storing node Q2 of the latch circuit LQ2 is connected to gate electrodes of the NMOS transistors N122 and N132. The inversion storing node /Q1 of the latch circuit LQ1 is connected to gate electrodes of the NMOS transistors N135 and N140. The storing node Q1 of the latch circuit LQ1 is connected to gate electrodes of the NMOS transistors N133 and N138. The inversion storing node /Q0 of the latch circuit LQ0 is connected to gate electrodes of the NMOS transistors N128 and N123. The storing node Q0 of the latch circuit LQ0 is connected to gate electrodes of the NMOS transistors N130, N125, and N120.
An NMOS transistor N151 is connected between the storing node Q2 of the latch circuit LQ2 and a bus line IO0. An NMOS transistor N152 is connected between the storing node Q1 of the latch circuit LQ1 and a bus line IO1. An NMOS transistor N153 is connected between the storing node Q0 of the latch circuit LQ0 and a bus line IO2. Gate electrodes of the NMOS transistors N151, N152, and N153 serving as column gates are connected to a supply line of a signal Y1.sub.-- 0.
The writing operation will now be described. In the standby mode, the signal PGM is set to the low level, the NMOS transistor N102 is held non-conductive, and the bit lines BL0 and BL1 are disconnected from the latch circuits LQ2, LQ1, and LQ0 of the bit line voltage generating circuit 112.
The signal DIS is set to the high level and the signals TRN, AiB, and AiN are set to (Vcc-Vth). The bit lines BL0 and BL1 are set to the ground level.
When the writing operation is activated in this state, the signal Y1.sub.-- 0 is set to the high level and the write data is fetched and held into the latch circuits LQ2, LQ1, and LQ0.
After that, the signal DIS is switched to the low level and the bit lines BL0 and BL1 are disconnected from the ground line. The signals TRN, AiB, and AiN are set to the high level (for example, passing voltage upon reading) that is equal to or higher than Vcc, the signal Vref is set to the low level. A PMOS transistor P101 is held conductive. Thus, all bit lines BL0 and BL1 are charged to the power voltage Vcc.
Upon writing, the address on the side that is not selected by the address signal, for example, AiN is set to the ground level and the signal PGM is set to the high level. The voltage VB3 is set to the highest voltage, the voltage VB2 is set to the second highest voltage, the voltage VB1 is set to the third highest voltage, and the voltage VB0 is set to the ground level.
When the write data is "00x" (x is equal to 0 or 1), the inversion nodes /Q2 and /Q1 of the latch circuits LQ2 and LQ1 are at the high level. Therefore, the NMOS transistors N103 and N104 are made conductive and the bit line BL0 is set to the voltage VB0 (ground level).
When the write data is "01x", the NMOS transistors N105 and N106 are made conductive and the bit line BL0 is set to the voltage VB1.
When the write data is "10x", the NMOS transistors N107 and N108 are made conductive and the bit line BL0 is set to the voltage VB2.
When the write data is "110", the NMOS transistors N109, N110, and N111 are made conductive and the bit line BL0 is set to the voltage VB3.
When the write data is "111", all of the paths from the voltages VB0 to VB3 are disconnected from the bit line. Therefore, the voltage of the bit line is held at the Vcc level.
After the selection bit line BL0 was set to the voltage according to the write data by the above processes, the word line is set to the writing voltage, the non-selection word line is set to the write passing voltage, and the data is written.
The verifying and reading operations will now be described with reference to FIG. 5.
In the verifying operation, each time the one writing operation is finished, the write checks of "000", "001", "010", "011", "100", "101", and "110" are performed.
In this example, the verification is performed in order from the data at a higher level. That is, the word line voltage is sequentially reduced to VVF7.fwdarw.VVF6.fwdarw.VVF5 VVF4.fwdarw.VVF3.fwdarw.VVF2.fwdarw.VVF1 and the verification is performed. The verifying operation will now be specifically explained.
First, the signal Vref is set to the low level and the PMOS transistor P101 is held conductive. The signal TRN is set to VTRN (VTRN=Vcc-Vth). The bit line voltage is charged to the level dropped from the level of the signal TRN by the threshold voltage Vth' with the back bias. After that, by cutting off the NMOS transistor HN101, the node SA is charged to the power voltage Vcc.
After the elapse of a predetermined time, the signal Vref is set to the voltage for enabling the current enough to compensate the leak current of the bit line to be supplied to the PMOS transistor P101. The voltage P5V is set to the word line of the non-selection memory cell. The voltage VVF7 is applied to the word line to which the selection cell is connected.
First, the verification of the write data "000" is performed.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VVF7 (Vth&gt;VVF7), since no current flows in the cell, the bit line voltage does not change, the node SA is held at the power voltage Vcc, and the NMOS transistors N115, N116, and N117 are held conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0, .phi.LAT2, and .phi.LAT6 are sequentially set to the high level.
For a period of time during which the signal .phi.LAT0 is at the high level, the NMOS transistor N118 is switched to the conductive state. At this time, since. the NMOS transistor N115 is conductive, the inversion node /Q2 of the latch circuit LQ2 is set to the low level and the node Q2 of the latch circuit LQ2 is inverted to the high level.
For a period of time during which the signal .phi.LAT2 is at the high level, the NMOS transistor N124 is switched to the conductive state. At this time, since the NMOS transistor N123 is conductive and the NMOS transistor N122 is switched to the conductive state (because the node of the latch circuit LQ2 has been inverted) and the NMOS transistor N116 is conductive, the inversion node /Q1 of the latch circuit LQ1 is set to the low level and the node Q1 of the latch circuit LQ1 is inverted to the high level.
For a period of time during which the signal .phi.LAT6 is at the high level, the NMOS transistor N134 is switched to the conductive state. At this time, the NMOS transistor N133 is switched to the conductive state and the NMOS transistor N132 is switched to the conductive state (because the nodes of the latch circuits LQ2 and LQ1 have been inverted), and the NMOS transistor N117 is conductive. Thus, the inversion node /Q0 of the latch circuit LQ0 is set to the low level and the node Q0 of the latch circuit LQ0 is inverted to the high level.
Consequently, when the threshold voltage Vth in the memory cell in which the write data is "000" is larger than the word line voltage VVF7 (Vth&gt;VVF7), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111". After that, upon rewriting, the bit line BL is set to the power voltage Vcc, the channel is boosted to the non-writing potential, and no data is written.
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VVF7 (Vth&lt;VVF7), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor HN101 is turned on, and redistribution of charges occurs. The electric potential of the node SA is set to (VTRN-Vth') that is almost equal to the bit line voltage. When the potential of the node SA is equal to (VTRN-Vth'), the NMOS transistors N115, N116, and N117 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0, .phi.LAT2, and .phi.LAT6 are sequentially set to the high level.
For a period of time during which the signal .phi.LAT0 is at the high level, the NMOS transistor N118 is switched to the conductive state. Although the NMOS transistor N118 is switched to the conductive state, since the NMOS transistor N115 is not made conductive at all, the inversion of the node of the latch circuit LQ2 does not occur.
For a period of time during which the signal. .phi.LAT2 is at the high level, the NMOS transistor N124 is switched to the conductive state. In this instance, since the NMOS transistor N122 is non-conductive (because the inversion of the node of the latch circuit LQ2 does not occur), the inversion of the node of the latch circuit LQ1 does not occur.
For a period of time during which the signal .phi.LAT6 is at the high level, the NMOS transistor N134 is switched to the conductive state. In this instance, since the NMOS transistor N133 is non-conductive and the NMOS transistor N132 is non-conductive (because the inversion of the nodes of the latch circuits LQ2 and LQ1 does not occur), the inversion of the node of the latch circuit LQ0 does not occur.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "000" is smaller than the word line voltage VVF7 (Vth&lt;VVF7), the latch data of the latch circuits LQ2, LQ1, and LQ0 does not change but is held to "000". Upon rewriting, the bit line voltage is set to the writing potential and the data is written.
Subsequently, the verification of the write data "001" is performed. In this instance, the selection word line voltage is set to VVF6.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VVF6 (Vth&gt;VVF6), since no current flows in the cell, the bit line voltage does not change, the node SA is held at the power voltage Vcc, and the NMOS transistors N115, N116, and N117 are held conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT5 and .phi.LAT1 are sequentially set to the high level.
For a period of time during which the signal .phi.LAT5 is at the high level, the NMOS transistor N131 is switched to the conductive state. At this time, the NMOS transistor N130 is conductive, the NMOS transistor N127 is conductive, and the NMOS transistor N116 is conductive, so that the inversion node /Q1 of the latch circuit LQ1 is set to the low level and the node Q1 of the latch circuit LQ1 is inverted to the high level.
For a period of time during which the signal .phi.LAT1 is at the high level, the NMOS transistor N121 is made conductive, the NMOS transistor N120 is conductive, the NMOS transistor N119 is switched to the conductive state, and the NMOS transistor N115 is conductive, so that the inversion node /Q2 of the latch circuit LQ2 is set to the low level and the node Q2 of the latch circuit LQ2 is inverted to the high level.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "001" is larger than the word line voltage VVF6 (Vth&gt;VVF6), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111". After that, upon rewriting, the. bit line BL is set to the power voltage Vcc, the channel is boosted to the non-writing potential, and no data is written.
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VVF6 (Vth&lt;VVF6), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor HN101 is turned on, and redistribution of charges occurs. The electric potential of the node SA is set to (VTRN-Vth') that is almost equal to the bit line voltage. When the potential of the node SA is equal to (VTRN-Vth'), the NMOS transistors N115, N116, and N117 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT5 and .phi.LAT1 are sequentially set to the high level.
For a period of time during which the signal .phi.LAT5 is at the high level, the NMOS transistor N131 is switched to the conductive state. In this instance, since the NMOS transistor N116 is not made conductive at all, the inversion of the node of the latch circuit LQ1 does not occur.
For a period of time during which the signal .phi.LAT1 is at the high level, the NMOS transistor N121 is switched to the conductive state. In this instance, since the NMOS transistor N119 is non-conductive, the inversion of the node of the latch circuit LQ2 does not occur.
Consequently, when the threshold voltage Vth of the memory cell in which the write data is "001" is smaller than the word line voltage VVF6 (Vth&lt;VVF6), the latch data of the latch circuits LQ2, LQ1, and LQ0 does not change but is held to "001". Upon rewriting, the bit line voltage is set to the writing potential and the data is written.
In a manner similar to the above, in case of the word line voltage VVF5, it is controlled in a manner such that only when the threshold voltage Vth of the memory cell in which the write data is "010" is larger than the word line voltage VVF5 (Vth&gt;VVF5), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111".
In case of the word line voltage VVF4, it is controlled in a manner such that only when the threshold voltage Vth of the memory cell in which the write data is "011" is larger than the word line voltage VVF4 (Vth&gt;VVF4), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111".
In case of the word line voltage VVF3, it is controlled in a manner such that only when the threshold voltage Vth of the memory cell in which the write data is "100" is larger than the word line voltage VVF3 (Vth&gt;VVF3), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111".
In case of the word line voltage VVF2, it is controlled in a manner such that only when the threshold voltage Vth of the memory cell in which the write data is "101" is larger than the word line voltage VVF2 (Vth&gt;VVF2), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111".
In case of the word line voltage VVF1, it is controlled in a manner such that only when the threshold voltage Vth of the memory cell in which the write data is "110" is larger than the word line voltage VVF1 (Vth&gt;VVF1), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111".
At the end of the verification at the word line voltage VVF1, the wired OR of the inversion signals of all latch data is calculated. If any one of them is equal to "0", the result of the wired OR is set to the low level and the processing routine advances to the rewriting process. If all of them are equal to "1", the writing operation is finished. The foregoing writing and verifying cycle is repeated until it is determined that the data has sufficiently been written into all of the memory cells or until the number of writing times reaches a predetermined value.
The reading operation will now be described with reference to FIG. 6. Upon reading, the reset signal RST is set to the high level for a predetermined period of time, thereby initializing the storing nodes Q2, Q1, and Q0 of the latch circuits LQ2, LQ1, and LQ0 to the low level. In a manner similar to the case of the verification, the data is read out in order from the data at a higher level. That is, the word line voltage is sequentially reduced to VRD7.fwdarw.VRD6.fwdarw.VRD5.fwdarw.VRD4.fwdarw.VRD3.fwdarw.VRD2.fwdarw.VR D1 and the data is read out.
Upon reading, in a manner similar to the case of the verification, first, the signal Vref is set to the low level, and the PMOS transistor P101 is held conductive. The signal TRN is set to VTRN (VTRN=Vcc-Vth). The bit line voltage is charged to the level dropped from the level of the signal TRN by the threshold voltage Vth' with the back bias. After that, by cutting off the NMOS transistor HN101, the node SA is charged to the power voltage Vcc.
After the elapse of a predetermined time, the signal Vref is set to the voltage which enables the current enough to compensate a leak current of the bit line to be supplied to the PMOS transistor P101. The voltage P5V is set to the word line of the non-selection memory cell. The voltage VRD7 is applied to the word line to which the selection cell is connected.
When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD7 (Vth&gt;VRD7) as a result of the reading at the word line voltage VRD7, since no cell current flows, the node SA is held at the power voltage Vcc. In this instance, the NMOS transistors N115, N116, and N117 are made conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0, .phi.LAT2, and .phi.LAT6 are sequentially set to the high level.
When the signal .phi.LAT0 is set to the high level, the NMOS transistor N118 is made conductive. Since the NMOS transistor N115 is conductive, the inversion node /Q2 of the latch circuit LQ2 is set to "0", and the node Q2 of the latch circuit LQ2 is inverted to "1".
When the signal .phi.LAT2 is set to the high level, the NMOS transistor N124 is made conductive. In this instance, the NMOS transistor N123 is conductive and the NMOS transistor N122 is switched to the conductive state. Since the NMOS transistor N116 is conductive, the inversion node /Q1 of the latch circuit LQ1 is set to "0" and the node Q1 of the latch circuit LQ1 is inverted to "1".
When the signal .phi.LAT6 is set to the high level, the NMOS transistor N134 is made conductive. In this instance, the NMOS transistors N133 and N132 are switched to the conductive state. Since the NMOS transistor N117 is conductive, the inversion node /Q0 of the latch circuit LQ0 is inverted to "0" and the node Q0 of the latch circuit LQ0 is inverted to "1".
Consequently, when the threshold voltage Vth. of the memory cell is larger than the word line voltage VRD7 (Vth&gt;VRD7), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "111".
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VRD7 (Vth&lt;VRD7), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor HN101 is made conductive, and redistribution of charges occurs. The voltage of the node SA is set to (VTRN-Vth') that is almost equal to the bit line voltage. Thus, the NMOS transistors N115, N116, and N117 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0, .phi.LAT2, and .phi.LAT6 are sequentially set to the high level.
When the signal .phi.LAT0 is set to the high level, the NMOS transistor N118 is made conductive. However, since the NMOS transistor N115 is not made conductive at all, the inversion of the node of the latch circuit LQ2 does not occur.
When the signal .phi.LAT2 is set to the high level, the NMOS transistor N124 is made conductive. However, since the NMOS transistor N122 is non-conductive, the inversion of the node of the latch circuit LQ1 does not occur.
When the signal .phi.LAT6 is set to the high level, the NMOS transistor N134 is made conductive. However, since the NMOS transistors N132 and N133 are non-conductive, the inversion of the node of the latch circuit LQ0 does not occur.
Subsequently, the word line voltage is set to VRD6 and the reading operation is performed. When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD6 (Vth&gt;VRD6) as a result of the reading at the word line voltage VRD6, since no cell current flows, the node SA is held at the power voltage Vcc. In this instance, the NMOS transistors N115, N116, and N117 are made conductive.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0 and .phi.LAT2 are sequentially set to the high level.
When the signal .phi.LAT0 is set to the high level, the NMOS transistor N118 is made conductive. Since the NMOS transistor N115 is conductive, the inversion node /Q2 of the latch circuit LQ2 is set to "0", and the node Q2 of the latch circuit LQ2 is inverted to "1".
When the signal .phi.LAT2 is set to the high level, the NMOS transistor N124 is made conductive. In this instance, the NMOS transistor N123 is conductive. The NMOS transistor N122 is switched to the conductive state. Since the NMOS transistor N116 is conductive, the inversion node /Q1 of the latch circuit LQ1 is set to "0" and the node Q1 of the latch circuit LQ1 is inverted to "1".
Consequently, when the threshold voltage Vth of the memory cell is larger than the word line voltage VRD6 (Vth&gt;VRD6), the latch data of the latch circuits LQ2, LQ1,and LQ0 is inverted to "110".
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VRD6 (Vth&lt;VRD6), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor HN101 is made conductive, and redistribution of charges occurs. The voltage of the node SA is set to (VTRN-Vth') that is almost equal to the bit line voltage. Thus, the NMOS transistors N115, N116, and N117 cannot be made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0 and .phi.LAT2 are sequentially set to the high level.
When the signal .phi.LAT0 is set to the high level, the NMOS transistor N118 is made conductive. Since the NMOS transistor N115 is not made conductive at all, however, the inversion of the node of the latch circuit LQ2 does not occur.
When the signal .phi.LAT2 is set to the high level, the NMOS transistor N124 is made conductive. However, since the inversion of the node of the latch circuit LQ2 does not occur, the NMOS transistor N122 is non-conductive. Therefore, the inversion of the node of the latch circuit LQ1 does not occur.
Subsequently, the word line voltage is set to VRD5 and the reading operation is performed. When the threshold voltage Vth of the memory cell is larger than the word line voltage VRD5 (Vth&gt;VRD5) as a result of the reading at the word line voltage VRD5, since no cell current flows, the node SA is held at the power voltage Vcc. In this instance, the NMOS transistors N115, N116, and N117 are held conductive.
The following cases are considered with respect to the latch data.
(1) When Vth&gt;VRD7: latch data is "111" PA1 (2) When VRD7&gt;Vth&gt;VRD6: latch data is "110" PA1 (3) When VRD6&gt;Vth&gt;VRD5: latch data is "000" PA1 n latch circuits in each of which write data is latched at the time of writing and, when the data is sufficiently written at the time of verification, it is set to predetermined data, and further, read data is set at the time of reading; PA1 write control means for setting into a bit line voltage according to the data latched in the latch circuit at the time of writing; PA1 verify control means for setting a word line voltage in accordance with a distribution state of the threshold voltage at the time of verification, specifying the latch circuit depending on whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not, and controlling so that when the data is sufficiently written at the time of the verification, predetermined data is set into the latch circuit; and PA1 read control means for setting the word line voltage in accordance with the distribution state of the threshold voltage at the time of reading, specifying the latch circuit depending on whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not, and controlling so that the read data is set into the latch circuit, PA1 wherein in the verifying operation, the verify control means sets the word line voltage to (2n-1) stages in accordance with the distribution state of the threshold voltage, controls so that the bit line is precharged or not in accordance with the data latched in the latch circuit, detects whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not on the basis of whether a current flows in the memory cell or not, and specifies the latch circuit in accordance with an output of the detection, thereby allowing the predetermined data to be set into the latch circuit when the data is sufficiently written at the time of the verification. PA1 n latch circuits in each of which write data is latched at the time of writing and, when the data is sufficiently written at the time of verification, it is set to predetermined data, and further, read data is set at the time of reading; PA1 write control means for setting into a bit line voltage according to the data latched in the latch circuit at the time of writing; PA1 verify control means for setting a word line voltage in accordance with a distribution state of the threshold voltage at the time of verification, specifying the latch circuit depending on whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not, and controlling so that when the data is sufficiently written at the time of the verification, predetermined data is set into the latch circuit; and PA1 read control means for setting the word line voltage in accordance with the distribution state of the threshold voltage at the time of reading, specifying the latch circuit depending on whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not, and controlling so that the read data is set into the latch circuit, PA1 wherein at the time of reading, the read control means sets the word line voltage to a plurality of stages in accordance with the distribution state of the threshold voltage, precharges the bit line only when an inversion of a node of the latch circuit had not occurred until the previous time, detects whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not on the basis of whether a current flows in the memory cell or not, and specifies the latch circuit in accordance with an output of the detection, thereby allowing the read data to be set into the latch circuit at the time of the reading. PA1 setting a word line voltage to a plurality of stages in-accordance with a distribution state of the threshold voltage; PA1 controlling so that the bit line is precharged or not in accordance with data latched in a latch circuit; PA1 detecting whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not on the basis of whether a current flows in the memory cell or not; and PA1 specifying the latch circuit in accordance with an output of the detection, thereby allowing predetermined data to be set into the latch circuit when the data is sufficiently written at the time of the verification. PA1 setting a word line voltage to a plurailty of stages in accordance with a distribution state of the threshold voltage; PA1 precharging the bit line only when an inversion of a node of the latch circuit had not occurred until the previous time; PA1 detecting whether the threshold voltage of the memory cell exceeds the voltage applied to the word line or not on the basis of whether a current flows in the memory cell or not; and PA1 specifying the latch circuit in accordance with an output of the detection, thereby allowing read data to be set into the latch circuit at the time of reading.
Only in the case of (3), it is necessary to construct such that the inversion of the nodes of the latch circuits LQ2 and LQ0 occurs and the read data becomes "101". At this time, it is necessary to construct such that no influence is exercised on the cases of (1) and (2).
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0 and .phi.LAT7 are sequentially set to the high level.
When the signal .phi.LAT0 is set to the high level, the NMOS transistor N118 is made conductive. Since the NMOS transistor N115 is conductive, the inversion node /Q2 of the latch circuit LQ2 is set to "0", and the node Q2 of the latch circuit LQ2 is inverted to "1".
In the cases of (1) and (2), since the node Q2 of the latch circuit LQ2 is inherently set to "1", there is no influence.
When the signal .phi.LAT7 is set to the high level, the NMOS transistor N136 is made conductive. In this instance, in the case of (3), the NMOS transistor N135 is conductive and the NMOS transistor N132 is switched to the conductive state. Since the NMOS transistor N117 is conductive, the inversion node /Q0 of the latch circuit LQ0 is set to "0" and the node Q0 of the latch circuit LQ0 is inverted to "1".
At this time, in the cases of (1) and (2), since the NMOS transistor N135 is made non-conductive, the inversion of the node does not occur.
Thus, when the threshold voltage Vth of the memory cell is larger than the word line voltage VRD5 (Vth&gt;VRD5), the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "101".
When the threshold voltage Vth of the memory cell is smaller than the word line voltage VRD5 (Vth&lt;VRD5), a cell current larger than the leak compensation current flows, the bit line voltage drops, the NMOS transistor HN101 is made conductive, and redistribution of charges occurs. The voltage of the node SA is set to (VTRN-Vth) that is almost equal to the bit line voltage. Thus, the NMOS transistors N115, N116, and N117 are not made conductive at all.
After the elapse of a predetermined time, the pulse-like signals .phi.LAT0 and .phi.LAT7 are sequentially set to the high level.
When the signal .phi.LAT0 is set to the high level, the NMOS transistor N118 is made conductive.
Since the NMOS transistor N115 is not made conductive at all, however, the inversion of the node of the latch circuit LQ2 does not occur.
When the signal .phi.LAT7 is set to the high level, the NMOS transistor N136 is made conductive. However, since the inversion of the node of the latch circuit LQ2 does not occur, the NMOS transistor N132 is non-conductive. Therefore, the inversion of the node of the latch circuit LQ0 does not occur.
In a manner similar to the above, the following control is performed. In case of the word line voltage VRD4, it is controlled so that the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "100" only when VRD5&gt;Vth&gt;VRD4.
In case of the word line voltage VRD3, it is controlled so that the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "011" only when VRD4&gt;Vth&gt;VRD3.
In case of the word line voltage VRD2, it is controlled so that the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "010" only when VRD3&gt;Vth&gt;VRD2.
In case of the word line voltage VRD1, it is controlled so that the latch data of the latch circuits LQ2, LQ1, and LQ0 is inverted to "001" only when VRD2&gt;Vth&gt;VRD1.
As shown in the foregoing two examples, when the storing level is converted into the quartic value or octenary value, a problem such that the circuit for verifying and the circuit for reading out become complicated and the circuit scale enlarges occurs. Particularly, upon verification, it is necessary to sequentially change the word line voltage and perform the verification with respect to only the memory cell of predetermined write data. The circuit construction for this purpose becomes complicated.
That is, in the example of the quartic value mentioned above, at the time of the verification, the word line is switched to VVF3 to VVF1 three times and, when the data is sufficiently written into the memory cell, the latch data is inverted to "11". This means that when the conditions such that the threshold voltage Vth of the memory cell is equal to or higher than the voltage applied to the word line and the write data is target data upon verification are satisfied, the latch data is inverted to "11".
For example, it is now assumed that in the memory cell in which the write data is "00", the data is not sufficiently written in the memory cell and a distribution 2 (refer to FIG. 8A) is obtained. It is also assumed that the word line voltage is simply compared with the threshold voltage and the latch data is inverted. When the word line voltage is sequentially switched to VVF3 to VVF1, if the word line voltage is set to VVF2, the latch data of the memory cell is inverted to "11" and the data is sufficiently written. If the occurrence of such a phenomenon is avoided, the circuit construction becomes complicated as mentioned above.
In the example of the octenary value mentioned above, upon verification, the word line is switched to VVF7 to VVF1 seven times and if the data is sufficiently written into the cell, the latch data is inverted to "111". This means that when the conditions such that the threshold voltage Vth of the memory cell is equal to or higher than the voltage applied to the word line and the write data is the target data upon verification are satisfied, the latch data is inverted to "111".
For example, it is assumed that in the memory cell in which the write data is "000", the data is not sufficiently written in the memory cell and a distribution 4 (refer to FIG. 14) is obtained. It is also assumed that the word line voltage is simply compared with the threshold voltage and the latch data is inverted. When the word line voltage is sequentially switched to VVF7 to VVF1, if the word line voltage is set to VVF4, the latch data of the memory cell is inverted to "111" and the data is sufficiently written. If the occurrence of such a phenomenon is avoided, the circuit construction becomes complicated as mentioned above.
In the examples of the quartic value and octenary value mentioned above, upon reading, the word line voltage is sequentially changed to VRD3 to VRD1 in the example of the quartic value and the word line voltage is sequentially changed to VRD7 to VRD1 in the example of the octenary value. While discriminating whether the threshold voltage of the memory cell has exceeded a predetermined level, the read data is decoded. In this case, it is necessary to hold the data in the latch circuit so as to prevent a situation such that the data which has once been decoded and held in the latch circuit is rewritten when the word line voltage is switched. If such a process is realized, the circuit construction becomes complicated as mentioned above.